The on-going demand for high performance electronic systems has driven the need for high-speed Very Large Scale Integration (VLSI) chips. VLSI implementations are demand driven to proceed in two inter-related directions: higher performance and higher density (more devices per unit area). While modern VLSI chips have achieved astonishingly high levels of performance and chip density the demand for even higher levels keeps growing.
A serious impediment to achieving higher performance and higher density is power consumption. As a general rule higher performance requires more power, which produces more heat, which increases failure rates which can render VLSI devices unsuitable for some tasks. The result is that power consumption is often the predominant challenge in improving high performance VLSI devices.
Almost all modern VLSI devices are clocked. As long as all gates can keep up the higher the clock rate the faster the performance. As clock rates and VLSI devices densities increase it becomes difficult to ensure that all gates can be properly clocked. One reason for this is that each sequential gate element in a VLSI device needs its own clock signal, but not all sequential gate elements are the same distance from the clock source. This means that all clock lines are not the same length and thus associated parameters such as distributed capacitances and resistances differ between elements. Different lengths coupled with unavoidable signal delays caused by distributed resistances and capacitances can cause clock signals to arrive at different elements at different times. This is referred to as clock skew.
Compounding VLSI clocking problems is that clocking requires power. In fact, the on-chip clock distribution network (CDN) of modern VLSI devices often consume more than 35% of the total device power and can occasionally require as much as 70%. This is expected since dynamic power is determined by:P=αCV2f
where α is the switching activity, C is the clock distribution network (CDN) capacitance, V is the supply voltage and f is the operating frequency.
Many works have attempted to reduce power consumption by decreasing one or more of these factors, but the savings are often limited during peak activity and the requirement that clock quality must not be degraded.
One successful approach to reducing VLSI power consumption is the use of Distributed LC resonant clocks. Referring now to FIG. 1, a distributed LC resonant clock network 2 circumvents problems by oscillating input energy 4 between electrical potentials and magnetic fields using a parallel clock capacitance Cclk 6 and an inductance L 8. An additional decoupling capacitance Cd 10 offsets the voltage range to 0-Vdd by forming a series LC tank with the inductance L 8.
The approach shown in FIG. 1 has proven the power savings of distributed LC resonant clocks. Distributed LC resonant clocks have also been shown to have stable clock phases and magnitudes when compared to alternative approaches such as standing waves and rotary/salphasic resonant clocks. Academic algorithms have further optimized distributed LC resonant clocks to show the possibility of power savings of up to 90%. Unfortunately, such large power savings come at the expense of relatively large inductors and decoupling capacitors.
Inductors such as the inductor 8 of FIG. 1 can be readily fabricated on-chip. For example, VLSI spiral inductors can be manufactured on-chip using well-known CMOS processes. For example, high-Q spiral inductors can be fabricated using modern processes with thick (˜10 μm) oxides. But, on-chip VLSI inductors come with parasitic resistances and capacitances that decrease the inductor quality factor. But parasitic resistances can be included in the model of the inductor, and parasitic capacitances can be treated as part of the decoupling capacitance in a resonant clock. FIG. 2 shows a square spiral inductor L 14 having an inductance that can be approximated as:
  L  =      0.0002    ⁢                  ⁢          l      ⁢                          〚                        ln          ⁢                                    2              ⁢              l                                      w              +              t                                      +        0.5        +                              w            +            t                                3            ⁢            l                              〛        ⁢                  ⁢    nH  
where n is the number of turns, w is the width of a trace, t is the thickness of the metal, l is the length of trace and s is the spacing between turns. Given n, s, w, di (inner diameter of the square spiral inductor), do (outer diameter of the square spiral inductor) the chip areas occupied by the inductor L 14 is:Area=d02=(di+2n(s+w))2 
On-chip capacitors are most effectively created as MOS (metal-oxide-semiconductor) capacitors that have both parallel-plate and fringe-field capacitances as illustrated by capacitor 20 shown in FIG. 3. The capacitance of capacitor 20 can be approximated as:
  C  =                    C        pp            +              C        fringe              =                                        e            di                                t            di                          ⁢        WL            +                        2          ⁢          π          ⁢                                          ⁢                      e            di                                    log          ⁡                      (                                          t                di                            H                        )                              
where W and L are the width and length of the metal representing the area of the capacitor, H is the height of the metal, and εdi and tdi are the permittivity and thickness of the dielectric layer. In the case of SiO2, εdi=εr ε0=3.9×8.854×10−12 F/m, where εr is the relative permittivity of the insulating material, and εo is the permittivity of free space.
As the W/H ratio reduces below unity the fringing capacitance of the capacitor 20 becomes dominate and significantly contributes to the overall capacitance. In a modern 90 nm CMOS technology, a MOS capacitor 20 can reach a capacitive density of 10˜20 fF/μm2.
These on-chip VLSI inductors and capacitors can be used to form a series or parallel LC “tank” circuit which resonates at a particular frequency. The resonant frequency fr of an ideal LC tank is the frequency when the network has zero total reactance. The resonant frequency of a tank (C and L) is ideally:
  fr  =      1          2      ⁢      π      ⁢              LC            
When the impedance of the LC tank is near infinite due to the reactances cancelling the drive capability requirement of the clock buffer is minimized and clock energy can be saved.
Referring once again to FIG. 1, the resonant clock topology contains two LC tanks: one parallel and one series. The parallel LC tank ideally has infinite impedance at resonance while the series impedance ideally has zero impedance. These tanks would counteract each other if they resonate at the same frequency. Therefore, the decoupling capacitor Cd 10 is typically much larger than Cclk 6 to separate the resonant frequencies of the parallel LCclk and extra series LCd tanks according to½π√{square root over (LCd)}<<½π√{square root over (LCclk)}
This ensures a wide margin such as fclk/fd˜3 by making Cd 10 for example 10 times Cclk 6 or more. The magnitude at the resonant frequency, w0=2πf0 is referred to as the characteristic impedance of the distributed LC resonant clock network 2.
In practice, the inductor L 8 area is the most significant obstacle to widespread acceptance of distributed LC resonant clock networks. Another problem is that the decoupling capacitance Cd 10 represents an extra burden on that acceptance. Reducing the inductor area and simplifying the decoupling capacitance would be highly beneficial and would make distributed LC resonant clock networks more practical.
Another issue with the wide spread acceptance of distributed LC resonant clock networks is achieving a configurable frequency of operation without significant efficiency degradation. Frequency scaling would be highly advantageous.
Therefore a distributed LC resonant clock network having reduced inductor dimensions would be beneficial. Even more beneficial would be a distributed LC resonant clock network having a simplified decoupling capacitance. Ideally such a distributed LC resonant clock network ideally would enable scalable frequency resonant clocks.